Invention Grant
US08363453B2 Static random access memory (SRAM) write assist circuit with leakage suppression and level control
有权
具有泄漏抑制和电平控制的静态随机存取存储器（SRAM）写辅助电路
- Patent Title: Static random access memory (SRAM) write assist circuit with leakage suppression and level control
- Patent Title (中): 具有泄漏抑制和电平控制的静态随机存取存储器（SRAM）写辅助电路
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Application No.: US12959883Application Date: 2010-12-03
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Publication No.: US08363453B2Publication Date: 2013-01-29
- Inventor: Igor Arsovski , Harold Pilo , Vinod Ramadurai
- Applicant: Igor Arsovski , Harold Pilo , Vinod Ramadurai
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent David A. Cain
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.
Public/Granted literature
- US20120140551A1 STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL Public/Granted day:2012-06-07
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