Invention Grant
- Patent Title: Scalable efficient I/O port protocol
- Patent Title (中): 可扩展的高效I / O端口协议
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Application No.: US10677583Application Date: 2003-10-02
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Publication No.: US08364851B2Publication Date: 2013-01-29
- Inventor: Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
- Applicant: Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F3/00
- IPC: G06F3/00

Abstract:
A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.
Public/Granted literature
- US20040073738A1 Scalable efficient I/O port protocol Public/Granted day:2004-04-15
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