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US08365056B2 Receiver equipped with a trellis viterbi decoder 失效
接收机配有网格维特比解码器

Receiver equipped with a trellis viterbi decoder
Abstract:
A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received including a series of symbols, is provided. The receiver comprises a programmable logic circuit that includes a source memory A and a destination memory B each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, and an operator able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory and destination memory.
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