A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.