Invention Grant
US08365127B2 Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
有权
基于布线图案的边界长度和密度，半导体设计装置和半导体器件处理虚设图案的方法
- Patent Title: Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
- Patent Title (中): 基于布线图案的边界长度和密度，半导体设计装置和半导体器件处理虚设图案的方法
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Application No.: US13450317Application Date: 2012-04-18
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Publication No.: US08365127B2Publication Date: 2013-01-29
- Inventor: Keisuke Hirabayashi
- Applicant: Keisuke Hirabayashi
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-003173 20070111
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.
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