Invention Grant
US08367473B2 Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
有权
具有暴露图案化电介质层的单一图案化金属层的衬底，包括衬底的芯片封装结构及其制造方法
- Patent Title: Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
- Patent Title (中): 具有暴露图案化电介质层的单一图案化金属层的衬底，包括衬底的芯片封装结构及其制造方法
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Application No.: US12779800Application Date: 2010-05-13
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Publication No.: US08367473B2Publication Date: 2013-02-05
- Inventor: Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee , Kuang-Hsiung Chen
- Applicant: Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee , Kuang-Hsiung Chen
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Priority: TW98126172A 20090804
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/786
Abstract:
A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.
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