Invention Grant
- Patent Title: Method to reduce trench capacitor leakage for random access memory device
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Application No.: US12680017Application Date: 2007-10-31
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Publication No.: US08367497B2Publication Date: 2013-02-05
- Inventor: Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- Applicant: Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- Applicant Address: US DE Wilmington
- Assignee: Agere Systems LLC
- Current Assignee: Agere Systems LLC
- Current Assignee Address: US DE Wilmington
- International Application: PCT/US2007/083176 WO 20071031
- International Announcement: WO2009/058142 WO 20090507
- Main IPC: H01L21/8242
- IPC: H01L21/8242 ; H01L27/108

Abstract:
A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
Public/Granted literature
- US20100264478A1 METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE Public/Granted day:2010-10-21
Information query
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