Invention Grant
US08367544B2 Self-aligned patterned etch stop layers for semiconductor devices
失效
用于半导体器件的自对准图案蚀刻停止层
- Patent Title: Self-aligned patterned etch stop layers for semiconductor devices
- Patent Title (中): 用于半导体器件的自对准图案蚀刻停止层
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Application No.: US12582137Application Date: 2009-10-20
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Publication No.: US08367544B2Publication Date: 2013-02-05
- Inventor: Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
- Applicant: Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Parashos Kalaitzis
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
Public/Granted literature
- US20110092069A1 SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES Public/Granted day:2011-04-21
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