Invention Grant
- Patent Title: Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device
- Patent Title (中): 互连基板,制造互连基板和半导体器件的方法
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Application No.: US12654017Application Date: 2009-12-08
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Publication No.: US08367939B2Publication Date: 2013-02-05
- Inventor: Kiminori Ishido
- Applicant: Kiminori Ishido
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-314114 20081210
- Main IPC: H05K1/16
- IPC: H05K1/16

Abstract:
Embodiments of the invention provide an interconnect substrate capable of improving the connection reliability and yield of a semiconductor device, a method of manufacturing the interconnect substrate, and a semiconductor device using the interconnect substrate. An interconnect substrate according to an embodiment of the invention includes: a substrate; an electrode pad formed over the substrate; an insulating film (solder resist film) formed over the substrate; an opening formed in the insulating film, in which the upper surface of the electrode pad is exposed on the bottom surface of the opening and a metal film formed over the upper surface of the electrode pad and side surface of the insulating film in the opening. At least a portion of the edge of an upper surface of the metal film is higher than the other portions of the upper surface of the metal film.
Public/Granted literature
- US20100139963A1 Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device Public/Granted day:2010-06-10
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