A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring. Also, the data linker includes the gate pattern connected to the data pad, the data pattern formed opposite to the gate pattern in the center of the gate insulation film, and the connection wiring configured to connect the gate pattern with the data pattern through a first contact hole which exposes the data pattern and the gate pattern by penetrating through the passivation film and the gate insulation film.