Invention Grant
- Patent Title: Multiple orientation nanowires with gate stack stressors
- Patent Title (中): 具有栅堆叠应力的多取向纳米线
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Application No.: US12505580Application Date: 2009-07-20
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Publication No.: US08368125B2Publication Date: 2013-02-05
- Inventor: Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
- Applicant: Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Agent Louis J. Percello
- Main IPC: H01L27/085
- IPC: H01L27/085

Abstract:
An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
Public/Granted literature
- US20110012176A1 Multiple Orientation Nanowires With Gate Stack Stressors Public/Granted day:2011-01-20
Information query
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