Invention Grant
- Patent Title: Fused buss for plating features on a semiconductor die
- Patent Title (中): 熔融母线用于半导体管芯上的电镀特征
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Application No.: US13189060Application Date: 2011-07-22
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Publication No.: US08368172B1Publication Date: 2013-02-05
- Inventor: George R. Leal , Kevin J. Hess , Trent S. Uehling
- Applicant: George R. Leal , Kevin J. Hess , Trent S. Uehling
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Mary Jo Bertani; Joanna G. Chiu
- Main IPC: H01L23/525
- IPC: H01L23/525

Abstract:
A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.
Public/Granted literature
- US20130020674A1 FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE Public/Granted day:2013-01-24
Information query
IPC分类: