Invention Grant
US08368172B1 Fused buss for plating features on a semiconductor die 有权
熔融母线用于半导体管芯上的电镀特征

Fused buss for plating features on a semiconductor die
Abstract:
A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.
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