Invention Grant
US08368195B2 Semiconductor device including arrangement to control connection height and alignment between a plurity of stacked semiconductor chips
失效
半导体器件包括用于控制堆叠的半导体芯片的纯度的连接高度和对准的布置
- Patent Title: Semiconductor device including arrangement to control connection height and alignment between a plurity of stacked semiconductor chips
- Patent Title (中): 半导体器件包括用于控制堆叠的半导体芯片的纯度的连接高度和对准的布置
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Application No.: US12652245Application Date: 2010-01-05
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Publication No.: US08368195B2Publication Date: 2013-02-05
- Inventor: Hisashi Tanie , Takeyuki Itabashi , Nobuhiko Chiwata , Motoki Wakano
- Applicant: Hisashi Tanie , Takeyuki Itabashi , Nobuhiko Chiwata , Motoki Wakano
- Applicant Address: JP Tokyo
- Assignee: Hitachi Metals, Ltd.
- Current Assignee: Hitachi Metals, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2009-000070 20090105
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.
Public/Granted literature
- US20100171209A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2010-07-08
Information query
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