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US08368423B2 Heterogeneous computer architecture based on partial reconfiguration 失效
基于部分重配置的异构计算机体系结构

Heterogeneous computer architecture based on partial reconfiguration
Abstract:
Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.
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