Invention Grant
- Patent Title: Semiconductor integrated circuit having an on-chip PLL and operating method thereof
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Application No.: US13358204Application Date: 2012-01-25
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Publication No.: US08368441B2Publication Date: 2013-02-05
- Inventor: Takahiro Kato
- Applicant: Takahiro Kato
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Womble Carlyle
- Priority: JP2011-067266 20110325
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal.
Public/Granted literature
- US20120242384A1 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN ON-CHIP PLL AND OPERATING METHOD THEREOF Public/Granted day:2012-09-27
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