Invention Grant
- Patent Title: Phase locked loop circuits and gain calibration methods thereof
- Patent Title (中): 锁相环路电路及其增益校准方法
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Application No.: US12490851Application Date: 2009-06-24
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Publication No.: US08368480B2Publication Date: 2013-02-05
- Inventor: Ping-Ying Wang
- Applicant: Ping-Ying Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.
Public/Granted literature
- US20100327984A1 PHASE LOCKED LOOP CIRCUITS AND GAIN CALIBRATION METHODS THEREOF Public/Granted day:2010-12-30
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