Invention Grant
US08368570B2 Method and system for calibrating column parallel ADCs 有权
校准列并行ADC的方法和系统

Method and system for calibrating column parallel ADCs
Abstract:
Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.
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