Invention Grant
- Patent Title: Method and system for calibrating column parallel ADCs
- Patent Title (中): 校准列并行ADC的方法和系统
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Application No.: US13018165Application Date: 2011-01-31
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Publication No.: US08368570B2Publication Date: 2013-02-05
- Inventor: Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
- Applicant: Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Main IPC: H03M1/06
- IPC: H03M1/06

Abstract:
Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.
Public/Granted literature
- US20120194368A1 METHOD AND SYSTEM FOR CALIBRATING COLUMN PARALLEL ADCS Public/Granted day:2012-08-02
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