Invention Grant
US08369135B1 Memory circuit with crossover zones of reduced line width conductors
有权
具有减少线宽导线的交叉区的存储电路
- Patent Title: Memory circuit with crossover zones of reduced line width conductors
- Patent Title (中): 具有减少线宽导线的交叉区的存储电路
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Application No.: US12960416Application Date: 2010-12-03
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Publication No.: US08369135B1Publication Date: 2013-02-05
- Inventor: Krishnakumar Mani
- Applicant: Krishnakumar Mani
- Applicant Address: US CA Santa Clara
- Assignee: Magsil Corporation
- Current Assignee: Magsil Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hahn and Moodley LLP
- Agent Vani Moodley, Esq.
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
A memory circuit comprising a set of longitudinal conducting lines and a set of transverse conducting lines, wherein, each conducting line comprises alternating regions of reduced and increased line widths. The set of transverse conducting lines overlies the set of longitudinal conducting lines to define crossover zones wherein the reduced line width regions of the transverse conducting lines cross over the reduced line width regions of the longitudinal conducting lines. The circuit further comprises addressable magnetic storage elements, each disposed within a crossover zone between a longitudinal conducting line and a transverse conducting line thereof. The reduced line width regions improve magnetic flux efficiency in the magnetic storage elements and the increased line width regions lower the resistance in the conducting lines.
Public/Granted literature
- US1385718A Weight-indicator for scales Public/Granted day:1921-07-26
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