Invention Grant
- Patent Title: Busy detection logic for asynchronous communication port
- Patent Title (中): 用于异步通信端口的繁忙检测逻辑
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Application No.: US13154348Application Date: 2011-06-06
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Publication No.: US08370543B1Publication Date: 2013-02-05
- Inventor: Syed Babar Raza , Pradeep Bajpai
- Applicant: Syed Babar Raza , Pradeep Bajpai
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F1/12 ; G06F1/00

Abstract:
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.
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