Invention Grant
- Patent Title: Buffer-aware routing in integrated circuit design
- Patent Title (中): 集成电路设计中的缓冲区感知路由
-
Application No.: US12823232Application Date: 2010-06-25
-
Publication No.: US08370782B2Publication Date: 2013-02-05
- Inventor: Chuck Alpert , Zhuo Li , Michael David Moffitt , Chin Ngai Sze , Paul G Villarrubia
- Applicant: Chuck Alpert , Zhuo Li , Michael David Moffitt , Chin Ngai Sze , Paul G Villarrubia
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Garg Law Firm, PLLC
- Agent Rakesh Garg; Libby Z. Toub
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.
Public/Granted literature
- US20110320992A1 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN Public/Granted day:2011-12-29
Information query