Invention Grant
- Patent Title: Misalignment correction for embedded microelectronic die applications
- Patent Title (中): 嵌入式微电子管芯应用的对准校正
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Application No.: US12830875Application Date: 2010-07-06
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Publication No.: US08372666B2Publication Date: 2013-02-12
- Inventor: Grant A. Crawford , Islam Salama
- Applicant: Grant A. Crawford , Islam Salama
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66

Abstract:
The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
Public/Granted literature
- US20120009738A1 MISALIGNMENT CORRECTION FOR EMBEDDED MICROELECTRONIC DIE APPLICATIONS Public/Granted day:2012-01-12
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