Invention Grant
- Patent Title: Semiconductor package fabrication process and semiconductor package
- Patent Title (中): 半导体封装制造工艺和半导体封装
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Application No.: US12685457Application Date: 2010-01-11
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Publication No.: US08372694B2Publication Date: 2013-02-12
- Inventor: Julien Vittu
- Applicant: Julien Vittu
- Applicant Address: FR Grenoble
- Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee Address: FR Grenoble
- Agency: Gardere Wynne Sewell LLP
- Priority: FR0952029 20090331
- Main IPC: H01L21/78
- IPC: H01L21/78

Abstract:
A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages.
Public/Granted literature
- US20100244229A1 SEMICONDUCTOR PACKAGE FABRICATION PROCESS AND SEMICONDUCTOR PACKAGE Public/Granted day:2010-09-30
Information query
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