Invention Grant
- Patent Title: Semiconductor integrated device and manufacturing method for the same
- Patent Title (中): 半导体集成器件及其制造方法相同
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Application No.: US12929870Application Date: 2011-02-22
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Publication No.: US08372704B2Publication Date: 2013-02-12
- Inventor: Hitoshi Okamoto
- Applicant: Hitoshi Okamoto
- Applicant Address: JP Kawasaki-Shi Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-313113 20071204; JP2008-298144 20081121
- Main IPC: H01L21/04
- IPC: H01L21/04

Abstract:
A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.
Public/Granted literature
- US20110143523A1 Semiconductor integrated device and manufacturing method for the same Public/Granted day:2011-06-16
Information query
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