Invention Grant
US08372705B2 Fabrication of CMOS transistors having differentially stressed spacers
有权
具有差分应力间隔物的CMOS晶体管的制造
- Patent Title: Fabrication of CMOS transistors having differentially stressed spacers
- Patent Title (中): 具有差分应力间隔物的CMOS晶体管的制造
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Application No.: US13013801Application Date: 2011-01-25
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Publication No.: US08372705B2Publication Date: 2013-02-12
- Inventor: Lahir Shaik Adam , Sanjay C Mehta , Balasubramanian S Haran , Bruce B. Doris
- Applicant: Lahir Shaik Adam , Sanjay C Mehta , Balasubramanian S Haran , Bruce B. Doris
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Louis J. Percello; Robert M. Trepp
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.
Public/Granted literature
- US20120187482A1 FABRICATION OF CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS Public/Granted day:2012-07-26
Information query
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