Invention Grant
- Patent Title: Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication
- Patent Title (中): 由反应金属层形成的集成电路的扩散势垒和制造方法
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Application No.: US11691167Application Date: 2007-03-26
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Publication No.: US08372739B2Publication Date: 2013-02-12
- Inventor: Tadahiro Ishizaka , Satohiko Hoshino , Kuzuhiro Hamamoto , Shigeru Mizuno , Yasushi Mizusawa
- Applicant: Tadahiro Ishizaka , Satohiko Hoshino , Kuzuhiro Hamamoto , Shigeru Mizuno , Yasushi Mizusawa
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Wood, Herron & Evans, LLP
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.
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