A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.