Invention Grant
- Patent Title: Interconnection structure and its design method
- Patent Title (中): 互连结构及其设计方法
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Application No.: US13015045Application Date: 2011-01-27
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Publication No.: US08373263B2Publication Date: 2013-02-12
- Inventor: Ryuichi Oikawa
- Applicant: Ryuichi Oikawa
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2010-016576 20100128
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate. The second power supply bonding wire is arranged in a position in which electromagnetic coupling between the second power supply bonding wire and the first signal bonding wire is smaller than electromagnetic coupling between the second power supply bonding wire and the first power supply bonding wire.
Public/Granted literature
- US20110180940A1 INTERCONNECTION STRUCTURE AND ITS DESIGN METHOD Public/Granted day:2011-07-28
Information query
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