Invention Grant
US08373274B2 Method of forming wiring structure and semiconductor device comprising underlying refractory metal layers
有权
形成布线结构的方法和包括下面的难熔金属层的半导体器件
- Patent Title: Method of forming wiring structure and semiconductor device comprising underlying refractory metal layers
- Patent Title (中): 形成布线结构的方法和包括下面的难熔金属层的半导体器件
-
Application No.: US12071089Application Date: 2008-02-15
-
Publication No.: US08373274B2Publication Date: 2013-02-12
- Inventor: Hisaya Sakai , Noriyoshi Shimizu
- Applicant: Hisaya Sakai , Noriyoshi Shimizu
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2004-064486 20040308
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/532
Abstract:
A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.
Public/Granted literature
- US20080142973A1 Method of forming wiring structure and semiconductor device Public/Granted day:2008-06-19
Information query
IPC分类:
