Invention Grant
- Patent Title: Wafer level chip scale package with reduced stress on solder balls
- Patent Title (中): 晶圆级芯片级封装,焊球应力减小
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Application No.: US13162394Application Date: 2011-06-16
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Publication No.: US08373282B2Publication Date: 2013-02-12
- Inventor: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
- Applicant: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L29/40

Abstract:
A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.
Public/Granted literature
- US20120319270A1 Wafer Level Chip Scale Package with Reduced Stress on Solder Balls Public/Granted day:2012-12-20
Information query
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