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Invention Grant
US08373452B2 Buffer circuit having switch circuit capable of outputting two and more different high voltage potentials 有权
具有能够输出两个以上不同的高压电位的开关电路的缓冲电路

Buffer circuit having switch circuit capable of outputting two and more different high voltage potentials
Abstract:
A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.
Abstract(Chinese):

缓冲电路包括接收第一电压的第一节点，接收低于第一电压的第二电压的第二节点，第三节点，驱动第一电压和第二电压的输出节点，耦合在第一节点和 所述输出节点，耦合在所述第二节点和所述输出节点之间的第二晶体管，所述第二晶体管的一端连接到所述第二节点，所述第二晶体管的另一端连接到所述第三节点，以及开关电路， 输出节点和第三个节点。 第一晶体管和开关电路都包括具有第一击穿电压的晶体管。 第二晶体管具有与第一击穿电压不同的第二击穿电压。

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