A phase-locked loop (PLL) frequency synthesizer includes a phase detector, a low pass filter coupled to the phase detector, an amplifier coupled to the low pass filter, a voltage controlled oscillator (VCO) coupled to the amplifier, a power splitter coupled to the VCO, and a switch configured to select between a first branch and a second branch through which to couple the power splitter to the phase detector. The first branch includes a frequency divider while the second branch includes a mixer. The PLL frequency synthesizer also includes a frequency accuracy indicator that compares a frequency in the first branch with a frequency generated in the second branch, and confirms that the PLL frequency synthesizer is locked to a desired frequency upon receiving a phase lock signal, if the frequency generated in the first branch is the same as the frequency generated in the second branch.