Invention Grant
- Patent Title: Digital phase-locked loop architecture
- Patent Title (中): 数字锁相环架构
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Application No.: US13264334Application Date: 2010-04-07
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Publication No.: US08373464B2Publication Date: 2013-02-12
- Inventor: Nicolas Sornin
- Applicant: Nicolas Sornin
- Applicant Address: GB Cambridge
- Assignee: Cambridge Silicon Radio Limited
- Current Assignee: Cambridge Silicon Radio Limited
- Current Assignee Address: GB Cambridge
- Agency: Novak Druce DeLuca + Quigg LLP
- Priority: GB0906418.9 20090414
- International Application: PCT/EP2010/054599 WO 20100407
- International Announcement: WO2010/118980 WO 20101021
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a delayed reference clock signal; a phase comparator (27) configured to generate a quantized signal indicative of the phase difference between the output signal and the delayed reference clock signal, an integrator (28) configured to integrate the quantized signal to form an integrated signal; a first feedback path (22) configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and a second feedback path (23) configured to adjust the delay applied by the delay cell (26) in dependence on the integrated signal.
Public/Granted literature
- US20120105120A1 Digital Phase-Locked Loop Architecture Public/Granted day:2012-05-03
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