Invention Grant
- Patent Title: Spur reduction technique for sampling PLL's
- Patent Title (中): 用于采样PLL的减速技术
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Application No.: US12973353Application Date: 2010-12-20
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Publication No.: US08373481B2Publication Date: 2013-02-12
- Inventor: Xiang Gao , Ahmad Bahai , Mounir Bohsali , Ali Djabbari , Eric Klumperink , Bram Nauta , Gerard Socci
- Applicant: Xiang Gao , Ahmad Bahai , Mounir Bohsali , Ali Djabbari , Eric Klumperink , Bram Nauta , Gerard Socci
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Andrew S. Viger; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
Public/Granted literature
- US20120154003A1 SPUR REDUCTION TECHNIQUE FOR SAMPLING PLL'S Public/Granted day:2012-06-21
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