Invention Grant
- Patent Title: Low-clock-energy, fully-static latch circuit
- Patent Title (中): 低时钟能量,全静态锁存电路
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Application No.: US13028023Application Date: 2011-02-15
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Publication No.: US08373483B2Publication Date: 2013-02-12
- Inventor: William J. Dally
- Applicant: William J. Dally
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Zilka-Kotab, PC
- Main IPC: H03K3/289
- IPC: H03K3/289

Abstract:
One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.
Public/Granted literature
- US20120206182A1 Low-Clock-Energy, Fully-Static Latch Circuit Public/Granted day:2012-08-16
Information query
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