Invention Grant
US08373493B2 Power switch design and method for reducing leakage power in low-power integrated circuits
有权
电源开关设计和降低低功耗集成电路泄漏功率的方法
- Patent Title: Power switch design and method for reducing leakage power in low-power integrated circuits
- Patent Title (中): 电源开关设计和降低低功耗集成电路泄漏功率的方法
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Application No.: US12882776Application Date: 2010-09-15
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Publication No.: US08373493B2Publication Date: 2013-02-12
- Inventor: Krishnendu Chakrabarty , Chrysovalantis Kavousianos , Zhaobo Zhang
- Applicant: Krishnendu Chakrabarty , Chrysovalantis Kavousianos , Zhaobo Zhang
- Applicant Address: US NC Durham
- Assignee: Duke University
- Current Assignee: Duke University
- Current Assignee Address: US NC Durham
- Agency: Saliwanchik, Lloyd & Eisenschenk
- Main IPC: H03K17/687
- IPC: H03K17/687

Abstract:
Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.
Public/Granted literature
- US20120062308A1 POWER SWITCH DESIGN AND METHOD FOR REDUCING LEAKAGE POWER IN LOW-POWER INTEGRATED CIRCUITS Public/Granted day:2012-03-15
Information query
IPC分类: