A PDP sustain driver circuit including at least one high voltage gate driver IC (HVIC) having a logic functional block. The PDP sustain driver circuit includes a signal buffer for receiving two input signals and providing the two signals to the logic functional block; and at least four switches including a charging switch, a discharging switch, a sustain switch and a grounding recovery switch, the HVIC providing a unique control signal from the logic functional block to the four switches to control said four switches.