A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal.