A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.