Phase and frequency recovery techniques comprising; a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, and receiver synchronization techniques (RST) enabling by one order more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of receivers oscillator.