Invention Grant
- Patent Title: Method and mechanism for implementing extraction for an integrated circuit design
- Patent Title (中): 实现集成电路设计提取的方法和机制
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Application No.: US12987064Application Date: 2011-01-07
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Publication No.: US08375342B1Publication Date: 2013-02-12
- Inventor: Eric Nequist , Richard Brashears , Matthew A. Liberty , Michael C. McSherry
- Applicant: Eric Nequist , Richard Brashears , Matthew A. Liberty , Michael C. McSherry
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.
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