Invention Grant
US08376237B2 Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device
有权
用于偏置EEPROM非易失性存储器阵列和相应的EEPROM非易失性存储器件的方法
- Patent Title: Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device
- Patent Title (中): 用于偏置EEPROM非易失性存储器阵列和相应的EEPROM非易失性存储器件的方法
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Application No.: US12885028Application Date: 2010-09-17
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Publication No.: US08376237B2Publication Date: 2013-02-19
- Inventor: Gianbattista Lo Giudice , Enrico Castaldo , Antonino Conte
- Applicant: Gianbattista Lo Giudice , Enrico Castaldo , Antonino Conte
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group PLLC
- Priority: EP09425359 20090918
- Main IPC: G06K19/06
- IPC: G06K19/06

Abstract:
Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
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