Invention Grant
- Patent Title: Manufacturing method of a semiconductor load board
- Patent Title (中): 半导体负载板的制造方法
-
Application No.: US13043463Application Date: 2011-03-09
-
Publication No.: US08377815B2Publication Date: 2013-02-19
- Inventor: Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen
- Applicant: Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen
- Applicant Address: TW Taoyuan
- Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee Address: TW Taoyuan
- Agency: Lin & Associates IP, Inc.
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.
Public/Granted literature
- US20120231621A1 Manufacturing Method Of A Semiconductor Load Board Public/Granted day:2012-09-13
Information query
IPC分类:
