Invention Grant
- Patent Title: Method of batch trimming circuit elements
- Patent Title (中): 批量修剪电路元件的方法
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Application No.: US12978492Application Date: 2010-12-24
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Publication No.: US08378460B2Publication Date: 2013-02-19
- Inventor: Peter J. Hopper , Peter Johnson , Peter Smeys , William French
- Applicant: Peter J. Hopper , Peter Johnson , Peter Smeys , William French
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/544 ; H01L21/66

Abstract:
Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.
Public/Granted literature
- US20120161294A1 Method of Batch Trimming Circuit Elements Public/Granted day:2012-06-28
Information query
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