Invention Grant
- Patent Title: Integrated circuit packaging system with stacking option and method of manufacture thereof
- Patent Title (中): 具有堆叠选择的集成电路封装系统及其制造方法
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Application No.: US12731870Application Date: 2010-03-25
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Publication No.: US08378476B2Publication Date: 2013-02-19
- Inventor: SeongMin Lee , SeongHun Mun , Byung Joon Han
- Applicant: SeongMin Lee , SeongHun Mun , Byung Joon Han
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent Mikio Ishimaru
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress.
Public/Granted literature
- US20110233747A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2011-09-29
Information query
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