Invention Grant
- Patent Title: Semiconductor package and semiconductor package module
- Patent Title (中): 半导体封装和半导体封装模块
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Application No.: US12833083Application Date: 2010-07-09
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Publication No.: US08378501B2Publication Date: 2013-02-19
- Inventor: Kosuke Yamada , Noboru Kato
- Applicant: Kosuke Yamada , Noboru Kato
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennett, LLP
- Priority: JP2009-173073 20090724
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52

Abstract:
A semiconductor package is provided with a functionally necessary minimum number of components with which stress concentrated on specific solder bumps is reduced and ruptures of the bumps are prevented even when stress caused by physical bending or a difference in thermal expansion coefficient is applied to the package. The semiconductor package includes a tabular die and bonding pads arranged on a mounting surface of the die. A passivation layer and a protective film are provided on the mounting surface such that central areas of the bonding pads are open. Under-bump metals (UBMs) connected to the bonding pads are provided in the openings, and solder bumps are provided on the surfaces of the UBMs. The diameter of the UBMs provided at corners of the die is less than that of the UBM provided at the approximate center of the die so that the elastic modulus of the UBMs provided at the corners is small.
Public/Granted literature
- US20110018130A1 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MODULE Public/Granted day:2011-01-27
Information query
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