According to one embodiment, a digital filter circuit includes an EXOR circuit, a clock gating circuit, a reset control circuit, a counter, a filter time setting circuit, a comparator, and a decoder. The clock gating circuit outputs a clock gating signal. The reset control circuit generates a first signal. The counter generates a count signal. The filter time setting circuit latches the count signal when the first signal is in the enable state, and outputs a latched count value as a second signal. The comparator receives the count signal and the second signal, and outputs a third signal of the enable state when the value of the count signal and the value of the second signal match each other.