Invention Grant
- Patent Title: Fast data weighted average circuit and method
- Patent Title (中): 快速数据加权平均电路及方法
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Application No.: US13233403Application Date: 2011-09-15
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Publication No.: US08378869B2Publication Date: 2013-02-19
- Inventor: Jeongseok Chae , Gábor C. Temes
- Applicant: Jeongseok Chae , Gábor C. Temes
- Applicant Address: JP Tokyo
- Assignee: Asahi Kasei Microdevices Corporation
- Current Assignee: Asahi Kasei Microdevices Corporation
- Current Assignee Address: JP Tokyo
- Agency: Maine Cernota & Rardin
- Main IPC: H03M3/00
- IPC: H03M3/00

Abstract:
A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.
Public/Granted literature
- US20120068865A1 FAST DATA WEIGHTED AVERAGE CIRCUIT AND METHOD Public/Granted day:2012-03-22
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