Various embodiments of a bit line precharge voltage generation circuit for a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a bit line precharge voltage generation circuit may include a voltage division block for dividing an internal voltage to generate a first division voltage and a second division voltage, wherein a level of the second division voltage is higher than a level of the first division voltage; a pull-up amplification block for comparing the level of the first division voltage with a level of a bit line precharge voltage on a bit line precharge voltage line, to raise the level of the bit line precharge voltage; and a pull-down amplification block for comparing the level of the second division voltage with the level of the bit line precharge voltage to lower the level of the bit line precharge voltage.