Invention Grant
- Patent Title: Structure and methods for measuring margins in an SRAM bit
- Patent Title (中): 用于测量SRAM位中边缘的结构和方法
-
Application No.: US13043229Application Date: 2011-03-08
-
Publication No.: US08379467B2Publication Date: 2013-02-19
- Inventor: Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
- Applicant: Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
Integrated circuit for performing test operation of static RAM bit and for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, the integrated circuit has a built-in self-test circuit for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
Public/Granted literature
- US20110158018A1 Structure and Methods for Measuring Margins in an SRAM Bit Public/Granted day:2011-06-30
Information query
