Invention Grant
US08379518B2 Multi-stage scheduler with processor resource and bandwidth resource allocation
有权
具有处理器资源和带宽资源分配的多级调度器
- Patent Title: Multi-stage scheduler with processor resource and bandwidth resource allocation
- Patent Title (中): 具有处理器资源和带宽资源分配的多级调度器
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Application No.: US11625884Application Date: 2007-01-23
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Publication No.: US08379518B2Publication Date: 2013-02-19
- Inventor: Deepak Kataria , Chengzhou Li
- Applicant: Deepak Kataria , Chengzhou Li
- Applicant Address: US PA Allentown
- Assignee: Agere Systems LLC
- Current Assignee: Agere Systems LLC
- Current Assignee Address: US PA Allentown
- Agency: Ryan, Mason & Lewis, LLP
- Main IPC: G01R31/08
- IPC: G01R31/08

Abstract:
A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.
Public/Granted literature
- US20080175270A1 Multi-Stage Scheduler with Processor Resource and Bandwidth Resource Allocation Public/Granted day:2008-07-24
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